PciTest Version: 2.39 PciTest.exe last created on Mar 15 2000 at 15:59:07 Command Line:"C:\HCT\TESTBIN\PCITEST.EXE" /X86 /CLASS07 /PCIPM /INTEGRATED INFO: Filtering on Class Code :0x07 Windows 9x (Windows 95) Build 3000, ****************************************************** Beginning test of device : HSP56 WDM COMMUNICATION DEVICE Bus: 0x000, Device: 0x01F, Function: 0x006 Reading the PCI Card's Config Space... Vendor ID: 0x8086, Device ID 0x2446 Class Code: 0x07, SubClassCode: 0x03, P/F 0x00 Verify that the Vendor ID is not zero or 0FFFFh (8086)...PASS Verify that the Subsystem Vendor ID is not zero nor 0xFFFF (1043)...PASS Verify that the Subsystem Device ID is not zero nor 0xFFFF (1466)...PASS Testing Read Only bits in SubSystem Vendor ID ...PASS SubSystem Vendor register is correctly Read Only Testing Read Only bits in SubSystem Device ID ...PASS SubSystem Device register is correctly Read Only Verify that the Interrupt Pin byte is 0,1,2,3,or 4 (02)...PASS Verify that the interrupt line byte is between 01h and 0Fh (09h)...PASS Verifying Read-Only bits in PCI Card Verifying PCI Read-only bits (0xFFFFFFFF) in Configuration Space (offset 0x00) Pass Verifying PCI Read-only bits (0x06FFFC00) in Configuration Space (offset 0x04) Pass Verifying PCI Read-only bits (0xFFFFFFFF) in Configuration Space (offset 0x08) Pass Verifying PCI Read-only bits (0x00FF0000) in Configuration Space (offset 0x0C) Pass Verifying PCI Read-only bits (0x00000001) in Configuration Space (offset 0x10) Pass Verifying PCI Read-only bits (0x00000001) in Configuration Space (offset 0x14) Pass Verifying PCI Read-only bits (0x00000001) in Configuration Space (offset 0x18) Pass Verifying PCI Read-only bits (0x00000001) in Configuration Space (offset 0x1C) Pass Verifying PCI Read-only bits (0x00000001) in Configuration Space (offset 0x20) Pass Verifying PCI Read-only bits (0x00000001) in Configuration Space (offset 0x24) Pass Verifying PCI Read-only bits (0x00000000) in Configuration Space (offset 0x28) Pass Verifying PCI Read-only bits (0xFFFFFFFF) in Configuration Space (offset 0x2C) Pass Verifying PCI Read-only bits (0x00000000) in Configuration Space (offset 0x30) Pass Verifying PCI Read-only bits (0xFFFFFFFF) in Configuration Space (offset 0x34) Pass Verifying PCI Read-only bits (0xFFFFFFFF) in Configuration Space (offset 0x38) Pass Verifying PCI Read-only bits (0xFFFFFF00) in Configuration Space (offset 0x3C) Pass Getting the resource Length... BAR is 0x0000E201, Length of BAR is 0xFFFF0100 Verify that Base Address Register 10's (I/O) bit 1 is 0(Reserved)...PASS INFO, IO space can only be located between 0x0000 0000 and 0x0000 FFFF Verify that Base Address Register I/O length is between 1h and 0x100 (00000100)...PASS Getting the resource Length... BAR is 0x0000E301, Length of BAR is 0xFFFF0080 Verify that Base Address Register 14's (I/O) bit 1 is 0(Reserved)...PASS INFO, IO space can only be located between 0x0000 0000 and 0x0000 FFFF Verify that Base Address Register I/O length is between 1h and 0x100 (00000080)...PASS Getting the resource Length... BAR is 0x00000000, Length of BAR is 0x00000000 Verify that Base Address Registers that are not used are 0...PASS Getting the resource Length... BAR is 0x00000000, Length of BAR is 0x00000000 Verify that Base Address Registers that are not used are 0...PASS Getting the resource Length... BAR is 0x00000000, Length of BAR is 0x00000000 Verify that Base Address Registers that are not used are 0...PASS Getting the resource Length... BAR is 0x00000000, Length of BAR is 0x00000000 Verify that Base Address Registers that are not used are 0...PASS WARNING: Extended capabilities not supported on this device (e.g. Power Management) Verify that we can WRITE to the IO Space bit (bit 0) of the command register...PASS! 00 24468086 02800005 07030003 00000000 0000e201 0000e301 00000000 00000000 20 00000000 00000000 00000000 14661043 00000000 00000000 00000000 00000209 40 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 60 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 a0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 c0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 e0 00000000 00000000 00000000 00000000 00000000 00000000 00000f47 00000000 8086 : (Vender ID) INTEL CORPORATION 2446 : (Device ID) This Device ID was unknown to Microsoft as of Nov 95 0005 : Command 0 (bit 9) Fast back-to-back enable 0 (bit 8) #SERR enable 0 (bit 7) Wait cycle control 0 (bit 6) Parity error response 0 (bit 5) VGA palette snoop 0 (bit 4) Memory write and invalidate enable 0 (bit 3) Special sycles 1 (bit 2) Bus master 0 (bit 1) Memory space 1 (bit 0) I/O space 0280 : Status 0 (bit 15) Detected Parity Error 0 (bit 14) Signaled System Error 0 (bit 13) Received Master Abort 0 (bit 12) Received Target Abort 0 (bit 11) Signaled Target Abort 01 (bits 10-9) DEVSEL timing 00-fast, 01-medium, 10-slow 0 (bit 8) Data Parity Error Detected 1 (bit 7) Fast Back-to-Back Capable 0 (bit 6) UDF Supported 0 (bit 5) 66 MHz Capable 0 (bit 4) Extended Capabilities Supported 0000 (bits 3-0) Reserved 03 : Revision ID 070300 : IDE Controller (see below) 0 (bit 7) Master IDE Device 000 (bits 6-4) Reserved 0 (bit 3) Programmable Indicator (Secondary) 0 (bit 2) Operating Mode (Secondary) 0 (bit 1) Programmable Indicator (Primary) 0 (bit 0) Operating Mode (Primary) 00 : Cache Line Size 00 : Latency Timer 00 : Header Type 00 : BIST PCI Device 0000e201 : I/O of length : -65280(ffff0100h) : First Base Address register 0000e301 : I/O of length : -65408(ffff0080h) : Second Base Address register 00000000 : Uninitialized : Third Base Address register 00000000 : Uninitialized : Fourth Base Address register 00000000 : Uninitialized : Fifth Base Address register 00000000 : Uninitialized : Sixth Base Address register 00000000 : Cardbus CIS Pointer 1043 : (SubSystem Vendor ID) (null) 1466 : SubSystem Device ID 00000000 : Expansion ROM Base Address 00000000 : Reserved 00000000 : Reserved 09 : Interrupt Line 02 : Interrupt Pin 00 : Min_Gnt 00 : Max_Lat ************************************************ Testing that the SubSystem ID's do not change after suspending / resuming Sleeping...Waking testing SubVendor/SubDevice ID's after suspend resume Testing HSP56 WDM COMMUNICATION DEVICE Verify that the Subsystem Vendor ID is not zero nor 0xFFFF (1043)...PASS Verify that the Subsystem Device ID is not zero nor 0xFFFF (1466)...PASS Testing Read Only bits in SubSystem Vendor ID ...PASS SubSystem Vendor register is correctly Read Only Testing Read Only bits in SubSystem Device ID ...PASS SubSystem Device register is correctly Read Only NTLOG REPORT ------------------------------------------------------- Tests Total 1 | Variations Total 1 ------------------------------------------------------------------ Tests Passed 1 100% | Variations Passed 1 100% /**** Time/Date/Name WrapUp ****/ Test Wrap-up Date: 3-12-2001 Test Wrap-up Time: 16:17:11 Test Name at Wrap-Up: Device Viewer / PCI Test /**** Time/Date/Name WrapUp ****/